status

Completed

year

2026

type

Technical Review Paper

Abstract

This technical review paper examines pipelining as one of the fundamental techniques used to improve processor throughput in computer architecture. The paper begins by explaining the limitation of sequential instruction execution, where a processor completes all stages of one instruction before starting the next, leaving many internal hardware units idle during different parts of execution. Pipelining addresses this limitation by dividing instruction execution into ordered stages and allowing multiple instructions to move through different stages at the same time. The review presents the classical five-stage RISC pipeline model, which includes instruction fetch, instruction decode, execute, memory access, and write back. Each stage is described according to its role in the instruction-processing flow, showing how pipelining increases hardware utilization and improves throughput without necessarily reducing the latency of a single instruction. The paper also explains the difference between latency and throughput, emphasizing that pipelining mainly improves the number of instructions completed per unit of time after the pipeline is filled. A major part of the review focuses on pipeline hazards, which are situations that interrupt the smooth flow of instructions and may cause stalls, flushing, or incorrect execution if not handled properly. The paper discusses data hazards, especially read-after-write dependencies, control hazards caused by branch and jump instructions, and structural hazards caused by hardware resource conflicts. To reduce the performance impact of these hazards, the review explains several common techniques, including forwarding, pipeline stalling, branch prediction, and instruction scheduling. Forwarding helps reduce data hazards by sending intermediate results directly between pipeline stages, while stalling preserves correctness when dependencies cannot be resolved immediately. Branch prediction reduces control-flow delays by guessing branch outcomes before they are fully known, and instruction scheduling rearranges instructions to reduce dependencies while preserving program meaning. The paper also discusses architectural considerations such as pipeline depth, stage balancing, hazard-handling hardware, and the trade-off between speed, cost, complexity, and correctness. Finally, the review highlights the main advantages and limitations of pipelining: it improves instruction throughput, increases processor resource utilization, supports instruction-level parallelism, and provides a foundation for advanced CPU techniques, but it also increases design complexity and can suffer from stalls, branch penalties, and dependency-related performance loss.